The present invention relates to a semiconductor device and the method of manufacturing the semiconductor device, and more particularly to a vertical field effect transistor and the method of manufacturing the vertical field effect transistor.
A vertical field effect transistor (hereinafter referred in to "vertical MOSFET") has been used over a variety of industrial fields in recent years because the vertical field effect transistor is simple in its drive circuit and can operate in a high-frequency region since it has excellent frequency characteristic, etc. The vertical field effect transistor is used over various fields, and thus demands increased performance has occurred. For example, demand for reduction of a resistant value (on-state resistance) during operation and reduction of a parasitic capacitance, as well as other characteristic has increased recently.
As a means for reducing the resistant value during operation, there has been proposed a structure in which a groove is defined in a wafer surface so that a portion in the vicinity of the groove is employed as a channel. An example of the vertical MOSFET of this type is introduced in ISPSD'93 pp. 135 to 140.
In this example, the groove is generally formed in the wafer surface through an Si etching process and an LOCOS (local oxidation of silicon) oxidizing process. As a method of manufacturing the conventional vertical MOSFET of this type, Japanese Patent Unexamined Publication No. Hei 7-321319 provides one example.
FIG. 9 is a cross-sectional view showing a structure of the conventional vertical MOSFET. Referring to FIG. 9, a wafer 110 is made up of an n.sup.+ -type semiconductor substrate 101 which is made of n.sup.+ -type silicon having an impurity concentration of approximately 10.sup.20 cm.sup.-3 and 100 to 300 .mu.m in thickness, and an n.sup.- -type epitaxial layer 102 which is allowed to epitaxially grow on the n.sup.+ -type semiconductor substrate 101 and made of n.sup.- -type silicon having an impurity concentration of approximately 10.sup.16 cm.sup.-3 and approximately 7 .mu.m in thickness. A plurality of unit cells that form vertical MOSFETs, respectively, are formed on a main surface of the wafer 110 (n.sup.- -type epitaxial layer 102 side) in the shape of a lattice.
On the main surface of the wafer 110, a U-shaped groove (hereinafter referred to as "U-groove") is formed in such a manner that a dimension from center to center of adjacent unit cells becomes about 12 .mu.m. The U-groove is formed by allowing a LOCOS oxide film to be formed on an inner wall of a groove which has been previously formed. Ions are implanted using the LOCOS oxide film as a mask and thermally diffused, an n.sup.+ -type source region 104 of about 1 .mu.m in depth and a p-type base region 103 of about 3 .mu.m in depth are formed in a self alignment manner, respectively.
The portion of the p-type base region 103 which is in the vicinity of the side wall of the U-groove is used as a channel 112.
A gate oxide film 105 of about 60 nm in thickness is formed on the inner wall of the U-groove and a gate electrode 106 of about 400 nm in thickness which is made of polysilicon is formed on the gate oxide film 105. Also, an interlayer insulation film 107 of about 1 .mu.m in thickness which is made of BPSG (boron phosphate silicate glass) is formed on the gate electrode 106.
Also, on a portion of the p-type base region 103, which is adjacent to the n.sup.+ -type source region 104, there is formed a p.sup.+ -type base contact region 109 of about 0.5 .mu.m in depth. A source electrode 108 which is formed on the interlayer insulation film 107 including aluminum, and the n.sup.+ -type source region 104 as well as a p.sup.+ -type base contact region 109 are in ohmic contact with each other through a contact hole 111, respectively. A drain electrode (not shown) is formed to be in ohmic contact with a rear surface of the n.sup.+ -type semiconductor substrate 101. A description will be given of a method of manufacturing the conventional vertical MOSFET shown in FIG. 9 follows using FIGS. 10A and 10B.
First, a silicon oxide film 60 and a silicon nitride film 63 of about 200 nm are deposited on the eptaxial layer 102 and are patterned to thereby form an opening pattern in the shape of a lattice which is perpendicular to and in parallel with a crystal face (011). Thereafter, etching is conducted on the silicon oxide film 60 using the silicon nitride film pattern as a mask to remove a part of the silixon oxide film 60 (a portion that forms a groove). Then, chemical dry etching is isotropically conducted to form a groove on the front surface of the n.sup.- -type epitaxial layer 102 as shown in FIG. 10A. It should be noted that a curve is formed on the opening portion of the groove.
Then, an inner wall of the groove is thermally oxidized with the silicon nitride film 63 as a mask as shown in FIG. 10B. This is a well-known LOCOS oxidation, and a selective oxide film, that is, an LOCOS oxide film is formed through the thermal oxidation at a normal LOCOS oxidation temperature, for example, 950-980.degree. C. At the same time, the n.sup.- -type epitaxial layer 102 is eroded by the LOCOS oxide film, to thereby form a U-groove. It should be noted that the curve formed through the chemical dry etching process still remains on the side wall of the U-groove as a curved portion 113. Also, the condition of chemical dry etching and the condition of LOCOS oxidation are set so that a face orientation of the channel 112 becomes a face close to (111). As a result, there are few defects, in particular, cristal defects, at an inner wall surface having the face (111) in U-groove.
Subsequently, boron ions are implanted in a self alignment manner with the LOCOS oxidation film as a mask, and thermal diffusion is conducted until the junction depth becomes about 3 .mu.m, to thereby form a p-type base region 103 (which is integral with the above p-type diffusion layer).
After the formation of the p-type base region 103, phosphorus ions are implanted using a resist film, formed by lithographic technology, and the LOCOS oxide film as masks. Next, thermal diffusion is conducted to create a function depth of approximately .+-.0.5 to 1.0 .mu.m, to thereby form the n.sup.+ -type source region 104.
In this example, to form the n.sup.+ -type source region 104, phosphorus ions are allowed to thermally diffuse deeper than the curved portion 113, which has been formed during the above chemical dry etching. The deep diffusion is used to prevent the flow of electrons from being interrupted as a result of electron accumulation at the curved portion 113.
Then, after the removal of the LOCOS oxide film through etching, the gate oxide film 105 of about 60 .mu.m in thickness is formed on the inner wall of the U-groove. Next, polysilicon of about 400 nm is deposited on the gate oxide film 105 and patterned to form the gate electrode 106. Subsequently, the p.sup.+ -type base contact region 109 is formed using a patterned resist film as a mask, and BPSG is allowed to grow on the main surface of the wafer 110, to thereby form the interlayer insulation film 107. Next, the contact hole 111 is opened in a part of the interlayer insulation film 107 which is above the n.sup.+ -type source region 104. The p.sup.+ -type base contact region 109,and the source electrode 108, including an aluminum film, are formed in such a manner so as to have ohmic contact with the n.sup.+ -type source region 104 and the p.sup.+ -type base contact region 109, respectively. Finally, the drain electrode (not shown), made of Ti/Ni/Au, is formed on the rear surface of the n.sup.+ -type semiconductor substrate 101.
In the vertical MOSFET thus manufactured, the n.sup.+ -type source region 104 and the p-type base region 103 are formed, respectively, in such a manner that the channel region 112 is formed in the portion deeper than the curved portion 113 of the side wall of the U-groove. Therefore, a flow of electrons is prevented from being accumulated on the curved portion 113, that is, such a MOSFET has a higher mobility of carriers. Accordingly, an on-state voltage of the vertical MOSFET becomes low (the on-state resistance becomes low).
However, in the above-mentioned conventional vertical MOSFET has a problem of large parasitic capacitance because the source region is formed deeper than the curved portion of the U-groove.
Further, there is a problem with the gate oxide film 105 being locally thinned at the curved portion and the electric field on the protrusion-shaped curved portion being concentrated. Therefore, the insulation breakdown voltage of the gate oxide film is reduced.